Problems with Verilog % Modulo and if-Statements

It is not tru that combinational block should not use always block.

In your case:

--- Quote Start ---

always @(iq,iStage)

begin

c <= (iq + 1'b1) % (1'b1<<(iStage));

end

--- Quote End ---

is a combinational block.

It can also be written without the always statement as:

--- Quote Start ---

assign c = (iq + 1'b1) % (1'b1<<(iStage));

--- Quote End ---

By the way, are you sure that shifting a 1 bit signal (1'b1) provides a signal with more than one bit?

Maybe that, if iStage is a two bit signal the maximum shift is three positions, the command should be:

--- Quote Start ---

assign c = (iq + 1'b1) % (4'b0001<<(iStage));

--- Quote End ---

Not sure about this however...