Problems with Verilog % Modulo and if-Statements

Hi all,

thanks for you help and your comments on my code. I think the code again needs some review and definitely needs to be done from a point of view which is more "hardware".

However, I do not fully understand what you mean by using combinational logic for doing the calculations.

So here's as far as I understood you:

1) The Calculations of a, b, and c should NOT be done in an "always" block

2) The if-statement is then executed in an "always" block triggered by the clock

What does that mean for me?

How can I create the calculation outside of the always statement?

Do I maybe even have to implement a module for each of the calculations?

How do I correctly trigger all this stuff?

By the way: What's the deal with the always blocks? Can I rely on the code being executed like e.g. in a C environment or does timing matter here?

In other words: is it guaranteed that the code is properly executed sequentially?

Thanks a lot!

Jonas Lindmann