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Honored Contributor
Honored ContributorProblems with Verilog % Modulo and if-Statements
Hi all, I got a problem with a normally relatively straightforward piece of Verilog code representing some modulo arithmetics and an if-statement. In the code below, the modulo of the r...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you need any more information, I'll be more than happy to supply. --- Quote End --- If you want to get an answer, post a compilable example that reproduces the problem (generating real logic, not something that's considered a fake by the compiler). One more point about the blocking statements. At least the statements generating the output from the sequential block should be non-blocking. Intermediate results assigned by blocking statements will effectively generate combinational logic in front of the final registered value. It's O.K., when you know, what you're doing and the timing is acceptable for your design.
