Problems with Verilog % Modulo and if-Statements

It looks like you calculate, in the same procedural block, the values for 'a' and 'b'. use these values to calculate 'c', use 'c' to decide what to do.

All is done using 'blocking' statement.

this is dangerous.

You should recode using:

1) non_blocking statement in describing circuits;

2) One procedural block for each signal.

3) separate sequential logic from combinational logic.

More practically. Use a combinational block that calculates c as a function of a and b.

use a sequential block that, when the clock edge arrives, decide what to do as a function of c value.

From what I know the use of blocking statements will probably cause difference between functional and gate level simulations.