Problems with Verilog % Modulo and if-Statements

Jonas,

Maybe it's because you stripped the code down to a small snippet. For me it seems you mix-up a program and a model. If there is an edge triggered block @(posedge wb_clk_i) and blocking assignments inside the block than in most cases there is this mix-up. I recommend to use non-blocking assigmnents and to keep in mind that all assignments execute in parallel. The if statement never takes the result from the aforementioned modulo operation at the same clock edge.

Harald