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Altera_Forum
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15 years ago

Problems with Verilog % Modulo and if-Statements

Hi all, I got a problem with a normally relatively straightforward piece of Verilog code representing some modulo arithmetics and an if-statement. In the code below, the modulo of the r...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi FvM,

Hi all,

thanks a lot for you quick reply. I think I didn't explain my actual problem in a proper manner...

To clarify:

This code was broken down to only show the core of the problem. In "real life", the registers ip, iq, and iStage will be fed from an external module. Thus, the values will of course change.

As already mentioned, the core problem is the modulo operation and the if-statement taking the result of the mod operation which appears when the registers take these very values hardwired in the code.

The comparison ==4'b0000 does somehow now work properly and always the code in the else statement is executed.

To clarify another point:

The two "OPTIONS" in the code should be exchanged. This is to clarify that if you use the result of the mod operation in the if statement, it doesn't work properly. However, if you hardwire the values, the if-statement works fine. So just (un)comment of the options and see the difference when it comes to the if-statement.

If you need any more information, I'll be more than happy to supply.

Thanks again,

Jonas