Problems with Verilog % Modulo and if-Statements

As written, the code generates no logic, because everything is constant and can be evaluated at compile time. And both set of constants refer to the first if case, at least with my Quartus version. Thus I assume that the code in your test has been different. Without knowing the real thing, I don't want to guess what happened.

As a more general comment, you're writing Verilog like sequential C code. Did you understand, how the generated logic will look like? The complete chain of blocking assignments has to be calculated in a single clock cycle by hardwired logic. That's possible for simple constructs, but not the usual way to write logic programs.

Most text books suggest to use nonblocking statements in sequential code (edge sensitive always blocks).