Problems with interfacing QDRII with NiosII on Stratix III devellopment board

Hi,

It's just one click away "Generate power-of-2 bus widths" on "Advanced Settings"

A good reference is the "External Memory Interface Handbook"

I'm also trying to use the QDR memory of Stratix III dev Kit, with NiosII and SOPC .

I still have issues with the top level connections of these pins, do we need another top level IP to drive them ?

.MEM_QDRII_afi_clk_out(),

.afi_cal_fail_from_the_MEM_QDRII(),

.afi_cal_success_from_the_MEM_QDRII(),

.afi_reset_n_from_the_MEM_QDRII(),

.dll_delayctrl_from_the_MEM_QDRII(),

.mem_doff_n_from_the_MEM_QDRII(),

.oct_rdn_to_the_MEM_QDRII(),

.oct_rup_to_the_MEM_QDRII(),

.pll_addr_cmd_clk_from_the_MEM_QDRII(),

.pll_afi_clk_from_the_MEM_QDRII(),

.pll_locked_from_the_MEM_QDRII(),

.pll_mem_clk_from_the_MEM_QDRII(),

.pll_write_clk_from_the_MEM_QDRII(),

Thanks