problems with inputs vs. constants

The code isn't really visual. :(

I found one place where asynchronous input signals can bring up illegal FSM states. It's related to the signals row and column (in fact very near to your initial post), that in return depends on the input signals UPDATE and RENA. If these signals are changed asynchronous to clock, curren_state can fall into a non-existing state encoding with multiple bits set. At worst case, it won't recover from this state without a reset.

Possible solutions:

- synchronizing all input signals, that are direct or indirect inputs to the next_state logic

- enforcing safe state machine encoding by synthesis attributes or settings.

Why can this happen? Consider that the state variable current_state is represented by multiple DFFs, one for each state according to the default one state hot encoding. Each DFF samples the input signals independently. If an input condition changes at the clock edge, it may be inconsistenly seen by the individual state bit DFFs. As a result, illegal state bit combinations can occur. Depending on the conditions in the state locgic, the FSM can be stuck in this illegal state. Safe state machine logic generates transitions to a legal state for all state bit combinations.