problems with inputs vs. constants

Thanks for your replies. kaz, I see your point. These input bits are from a bus external to the FPGA and registered in a bdf file before being taken into the VHDL code. It seems like the synthesizer should simply see these values as the q port of a DFF that goes to the outside world. Indeed, I tried bringing the register into the VHDL and that didn't work either.

In this situation, I want the constants to be there as a setting in one mode, and then have a user mode that is variable, so not just for testing. It should synthesize as a busmux.

FvM, I am still trying to track down what the "crash" really is myself. What happens is that when I run with RENA turned off, my PC console application can read and write the Xval and Yval registers (that I mentioned are external to the VHDL), but when the RENA bit is set, the console application indicates that the register is no longer writable. Bringing the q port of that register to the logic analyzer shows that the register is actually being updated. I expect you are right about the state machine being the problem, and honestly I don't know enough about VHDL state machines to know how they handle variable inputs.

There are outputs to the full code, and is synthesizable, but I just cut and pasted excerpts for simplicity since the entire file is rather large. Also, speaking of simulation, I still use Quartus 9.0 since I haven't had the time to face the learning curve on the ModelSim simulator. The code simulates fine on the old Simulator Tool.