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Altera_Forum's avatar
Altera_Forum
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14 years ago

problems with inputs vs. constants

Hi all, I am having problems using Input ports to control a function in VHDL. I think it may be a synthesis problem, but I am not sure. I could just not be understanding something or doing som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Nevertheless, it's legal VHDL code. You didn't tell what crashing of FSM means. I would expect the problem in the state machine code.

P.S.: You also didn't clarify, how you tested that code. What you show is an entity without any output signals that synthesizes to nothing, so you are talking apparently about a ModelSim simulation. I assume, that the variable inputsh ave been stimulated somehow.