Problems with a basic QSYS PCIe-DMA-Design. Timing not met.

Hello to all.

I'm trying to build up a basic design for future purposes. I derived it as good as I could from the PCIe in QSYS Design Example.

My goal was also to build it with an schematic-file as top-level-entity. And I wanted to use only the PCIe-RefClk for the whole Design (Is this possible).

You can see my results in the attached project.

What I have done so far:

- I built a QSYS-System with the PCIe-HIP, mSGDMA with Read- and Write-Master, a dummy FiFo connected to the DMA-Cores and a PIO for Resetting single components.

- I generated the QSYS-System and made a BSF-File

- I build a schematic-file with a PLL, the AltGX_Reconfig-Block and the QSYS-System inside and wired them there.

- I added the RX- and TX-Pins and the PCIe_Reset-Pin and wired then to the PCIe-HIP. The PCIe-RefClock-Pin feeds the InClk of the PLL and the PCIe-RefClk-Input of the PCIe-PIN

- I generated a basic SDC-File.

Then I compiled it all.

The Result:

Two times "Timing requirements not met.". The source of this is the PCIe-HIP<blabla>coreclkout

If you want to help me, you just have to unpack the attached Project, open the QSYS-File and generate it, and then compile the whole Design.

I know, resetting the PLL which feeds the PCIe-Core from the PCIe is a REALLY BAD IDEA!! But Hey, perhaps I wanted to get a Design which i could destroy if I want to ;-)

The basic Files:

- QSYS.qsys : my QSYS-System (Somehow obvious, right?)

- Top_Schematic.bdf : The Top-Entity

- sdc-add.sdc : A SDC-File which I use to generate the final SDC-File.

- PCIe-DMA-Startdesign.sdc : The final SDC-File used in my design

The IP-Cores:

- In the Folder "ip" : The three Altera IPs for DMA

- GX-Reconfig : The Alt_GX_Reconfig-Block used in Top-Entity

- PLL_0 : The PLL for generating a 50MHz (c0) and 125MHz (c1) clock for the QSYS-System

- Further IP-Cores : All from Altera listed in the QSYS-System (PCIe, OnChip-FiFo ....)

Now my question:

What am I doing wrong? Must I connect something else? Are the Connectionw wrong? Do I have to constrain something? I just don't get it.

Please be gentle, dummy at work.

Yours

Steffen