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Altera_Forum's avatar
Altera_Forum
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12 years ago

Problems with a basic QSYS PCIe-DMA-Design. Timing not met.

Hello to all. I'm trying to build up a basic design for future purposes. I derived it as good as I could from the PCIe in QSYS Design Example. My goal was also to build it with an schematic-file...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think I located the problem:

I changed the reference design for CycloneIV with a PCIe Gen1 1 Lane to my target device. And voilla: the Timings here also didn't meet.

So it's not a problem of my Design. I think my Device has a Speed Grade which is too low.

But I wonder why there can be a FPGA with a PCIe-HIP than can never ever meet the Timing Requirements. (Well, OK, the Fast Timing Model can have a functional Timing.)