Problems on Cyclone's reset value

It's a very basic logic design rather than a Cylone problem.

Consult the Quartus software manual about the methods to release an asynchronous reset synchronously. Generally, applying an asynchronous reset while the clock is yet running often results in unxpected behaviour due to timing violations on reset realease.

Thanks for replying~~~ :)

But in my design I did pass the reset signal through a series of Dffs, and then "or"ed the original "reset" and synchronized "reset" to make a safe reset signal for internal use. As far as I know, this approach can reliably remove metastability and unexpectancy on reset release, and this is how I did reset for ASIC designs. I think it should also work for FPGA designs, am I right?

Also, note that if I use "integer cnt" instead of "reg [3:0] cnt", the counter can be correctly reset to expected value upon reset, on the same PCB board using the same reset. Can anyone tell me what makes the difference between "reg"s and "integer"s?

btw, which chapter in Quartus software manual talked about the Altera methods to release an asynchronous reset synchronously? I don't remember reading about this in the manual -_-

Thanks & Danke!