Problem with WHILE Loop

Make sure you read the handbook on Moedlsim:

http://www.altera.com/literature/hb/qts/qts_qii53001.pdf

There are two flows:

1) Functional simulation, which is probably what you want to do(many designers just do functional sims and static timing analysis). With functional simulation, all the code is directly read into Modelsim and Quartus does not need to be called.

2) Timing simulation. This is where you synthesize your design into a part and then export HDL files(a .vho or .vo) and a timing file(.sdo). These are then read into Modelsim. But your testbench still goes into Modelsim directly and does not get used by Quartus.

For the record, your while loop is probably getting synthesized into a state-machine or something, which is basically tens of thousands of states, which basically will be a huge number of gates, which is what you do not want.