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Altera_Forum
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14 years ago

Problem with Triple Speed Ethernet sdc file

I met a problem where I compiled my design with the TSE IP core. The sdc file generated with the core use get_ports in the create_clock command. But my design instantiated the IP in my desig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

So I also have run into somewhat similar issues. I have instantiated a TSE MAC in a .qsys design file that is instantiated in another .qsys design file as a subsystem. Now I see some warnings related to the constraints in quartus, and would like to fix them.

Warning (332174): Ignored filter at pdq_nif_tse_mac_constraints.sdc(155):

clk could not be matched with a port

Warning (332174): Ignored filter at pdq_nif_tse_mac_constraints.sdc(158):

ff_tx_clk could not be matched with a port

Warning (332174): Ignored filter at pdq_nif_tse_mac_constraints.sdc(159):

ff_rx_clk could not be matched with a port

But how do I fix such issues as these clocks do not go in or out of the TSE IP AFAICT. I have an embedded FIFO in the TSE. I don't know if clk might be the receive clock wire or the transmit clock wire on the TSE MAC block. It doesn't seem to be either, but what clock is it?

Furthermore, I see some related issues like this one also.

Warning (332174): Ignored filter at timedDataSys_nif_tse_mac_constraints.sdc(162):

tx_clk could not be matched with a port

Now this one maybe I can fix because of course the tx clock is in the TSE's conduit and maybe I could rename the top level clock from ethernet_tx_clock to tx_clk but this appears to be a bad type of name to use and certainly isn't very maintainable in a large design; what for example does one do if we have two TSE's instantiated?

Furthermore, I see also advice in the TSE MAC documentation to modify the pdq_nif_tse_mac_constraints.sdc file, but should I really be doing that given that this is a QSYS generated file? Does one un-click the "generate HDL" option after making such changes? Is that a common practice? That doesn't appear to be very user friendly because my changes will of course be lost if I change the interface to my block.

So I am looking all around in QSYS for a way to rename the conduit component signals coming out of a block according to a hierarchical naming scheme, but cant find anything?

I am using Qsys 11.1sp2 Build 259.