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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with Stratix IV m9k mem read

Hi, I'm facing a strange problem with one of the FIFO reads (FIFO used for transferring data from one clock domain to another) - The problem is that, the very first datum is NOT getting written...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Thanks for the quick reply.

I have the read logic as

assign rd_data = mem[rd_ptr];

..not as a clocked process.

I'm not sure if this could be a problem.