Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Problem with Stratix IV m9k mem read

Hi, I'm facing a strange problem with one of the FIFO reads (FIFO used for transferring data from one clock domain to another) - The problem is that, the very first datum is NOT getting written...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As long as there is no timing violation reported there shouldn't be any problem. AFAIK there can be any skew between the two clocks.

Are you sure that you use the read clock correctly in your code? The read operation should be in an
always @(posedge rd_clk)
block, which doesn't show on your first post.

Now that I think about it, your waveforms are consistent with a read only done on the rising edge of wr_clk.