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Altera_Forum
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15 years ago

Problem with Stratix IV m9k mem read

Hi, I'm facing a strange problem with one of the FIFO reads (FIFO used for transferring data from one clock domain to another) - The problem is that, the very first datum is NOT getting written...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Yes. The read clock is twice as fast as write clock.

The design is properly constrained and there are no violations reported by the tool.

Is there any restriction with the memory unit for the skew requirement for write and read clocks?

If so, then is there any possibility of write getting blocked, when skew violation occur?