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Honored Contributor
Honored ContributorProblem with Stratix IV m9k mem read
Hi, I'm facing a strange problem with one of the FIFO reads (FIFO used for transferring data from one clock domain to another) - The problem is that, the very first datum is NOT getting written...
Altera_ForumHonored Contributor
Honored ContributorThere isn't any read clock on your waveforms, but I'm guessing that the read clock is twice as fast as the write clock?
It could be a timing problem. Is your design properly constrained and does it meet timing requirements?
