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Altera_Forum's avatar
Altera_Forum
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7 years ago

Problem with Quartus and PIN plan (EP4CE6)

I am currently working with FPGA as part of a course at the university. At the university we use Terasic Altera Cyclone III EP3C16 Development & Education boards, I am quite familiar with it, I can f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

1. I thought that I can use those switches for input in my schemes, not JTAG settings since this is written in schematic:

https://image.ibb.co/fyKG4y/Screen_Shot_2018_07_02_at_2_16_57_AM.png

And this is the only thing I found about JTAG and AS:

https://image.ibb.co/kD89Py/Screen_Shot_2018_07_02_at_2_17_06_AM.png

2. Thank you very much for this, I understand how to do this and it will be an easier problem to solve when I put everything into place to work properly.