Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Problem with PLL in EP1C12 device

Hello everyone, long time no see =] Recently I've built my own evaluation board with EP1C12 Cyclone device (yes, it's an old one, but I obtained it for free). The board is working, I can config...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I can't see, if the PLL Megafunction is configured correctly, but the clock divider is hold in reset by this line, so no output can be expected. 

div_rst <= PLL_lock and nrst;

P.S.: O.K., I see it's actually ndiv_rst, it should work then. The division factor is 21 in your design, resulting in 4.76 MHz output clock with 100 MHz input. Do you see a locked state?