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Altera_Forum's avatar
Altera_Forum
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13 years ago

Problem with PFL Simulation

Hi,

After reading the other posts regarding Parallel Flash Loader (PFL) simulation, I'm still having an issue getting mine up and running.

The problem I run into is that if I include the altera_mf library, as stated in the PFL User Guide, my simulation loads correctly, but I noticed that the altparallel_flash_loader module in the library is a stub; it doesn't contain a model or RTL. Therefore, my sim never goes anywhere, since the PFL is not operating.

There's also a source VHDL file in the libraries/ folder (altparallel_flash_loader.vhd) which I've tried to also include in my simulation, but since it has the same name as the module in altera_mf, whichever one is loaded second overrides the first. If I just load the source RTL file by itself, I get a series of "Unresolved defparam reference" errors, which I believe is due to the fact that I'm working in Verilog and the source RTL file is in VHDL.

The PFL User Guide implies both files need to be loaded, but I'm not sure how to properly load/link the files together to get a working PFL. Does someone have suggestions for create a .do file or testbench? I've attached mine for reference.

Thanks!

Matt

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    PFL simulation is tricky, apart from using the PFL itself, it must have stimulus from the flash device (which requires you to get the behavioral model from the flash vendor or you write it yourself).

    PFL simulation from RTL itself is kinda problematic because megafunction only generates the wrapper file in VHDL or verilog based on user's choice but the codes from the lower hierarchy are in verilog.

    maybe you could try simulating from the post-synthesis netlist (still functional simulation).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    That worked perfectly! After getting the post-synthesis netlist compiled, I was able to run my sim and finally find out my issue (bad option bits setting). Thanks!

    Matt