Problem with PFL Simulation

PFL simulation is tricky, apart from using the PFL itself, it must have stimulus from the flash device (which requires you to get the behavioral model from the flash vendor or you write it yourself).

PFL simulation from RTL itself is kinda problematic because megafunction only generates the wrapper file in VHDL or verilog based on user's choice but the codes from the lower hierarchy are in verilog.

maybe you could try simulating from the post-synthesis netlist (still functional simulation).