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Altera_Forum's avatar
Altera_Forum
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10 years ago

Problem with Partial Word Access from HPS

when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

Background:

In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

I am responsible for the board and FPGA design. Another software engineer is developing software under DS5 environment.

Avalon MM Slave interface is use on FPGA side.

Problem description:

Everything works fine on System Console. However, partial word access does not work on DS5, if the address is not multiple of 4.

for example, it works for address 0x800, but not for address 0x802.

Troubleshooting being conducted:

I thought it relates to where the data should be put on the 32bit data bus. So I revised FPGA code to duplicate the data on the 32-bit bus, but DS5 still reads all zeros.

Also tried to run SignalTap to capture waveforms, but DS5 and SignalTap cannot be run at the same time through the same JTAG connector.

anybody know what could be the problem?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The problem has been solved.

    The byteenable signal behaves differently when accessing from HPS than from System Console.

    When accessed from System Console, byteenable is asserted right for the entire transaction.

    When accessed from HPS (as observed on DS-5), byteenable is only asserted right for one clock cycle, then changed to 1111.

    This caused problem on my FPGA code. My code assumes that the byteenable will not change during the entire transaction.

    I revised the FPGA code to latch byteenable signal and the problem is solved.

    Thanks everybody for reading this post.