Forum Discussion
Update on the problem specified above. What I have discovered was there is a command being issued to the nios from our host computer which is requesting a software reset. The software was pointing all the way back to reloading the bsp. And, apparently, when this occurred, occasionally the CFM and the UFM content was being affected and prevented the image to function. For the short term, the nios will respond to the software reset command with an acknowledge character and nothing else. Since having that change made to the software, there have been no more problems with FPGA image being altered. Thanks to Anand Raj Shankar for responding to the earlier post. Even though I looked into all of your suggestions prior to the post. Having additional thoughts are always good.