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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem with GPIO assignments for the DE2

I have a feeling this might be some kind of bug? I'm running Quartus 11.0. I am using the GPIO_0 for various inputs and outputs and connecting my VHDL entities to the GPIO pins on a top level B...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How does the RTL look:

Bidirectional pins need to be defined in the RTL for the pin-planner to connect them properly.

IE:

for verilog they would be defined some like:

...

inout [15:0] GPIO_0,

...

assign GPIO_0 = OE_logic_c ? GPIO_r : 'bz; // Tristates the outputs, sets direction as input

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