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Altera_Forum
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14 years ago

Problem with Gigabit Ethernet Clocks

Hi, I am working in a design that includes a propietary MAC layer to the PHY Marvell Ethernet chip, using RGMII interface. The FPGA that I used to the design is a ARRIA GX II 260. I have define...
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Altera_Forum
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14 years ago

Daixiwen, I have revised the report that you said but I didn't find any information about the RGMII transmission pins. The RGMII reception pins (RXD and RX_CTL) are present in the I/O report, but the transmission (TXD and TX_CTL) pins did not appear in this report.

Socrates, could you explain a little more your last comment? I don't understand it because my problem is constraining the pins, not the clocks.

I have revised the SDC definition and I didn't find any problem. Thank you so much for your help.

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