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Altera_Forum
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14 years ago

Problem with Gigabit Ethernet Clocks

Hi, I am working in a design that includes a propietary MAC layer to the PHY Marvell Ethernet chip, using RGMII interface. The FPGA that I used to the design is a ARRIA GX II 260. I have define...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Clocks are not included in the path between DDRIO and FPGA pins, because clock is also generated using DDR primitives afaik (I am not sure actually).