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Altera_Forum
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14 years ago

Problem with Gigabit Ethernet Clocks

Hi, I am working in a design that includes a propietary MAC layer to the PHY Marvell Ethernet chip, using RGMII interface. The FPGA that I used to the design is a ARRIA GX II 260. I have define...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

First of all, thank you for your answer.

I have defined the clocks propertly, and the Timequest shows me that the definitons are OK (in the Report SDC I could see the clocks involved in the RGMII tranmission), but ther isn't any report of this clocks and the path between the output of Dobule Data Rate Registers and the pins of the PHY Layer.

Thanks

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