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Altera_Forum
Honored Contributor
Honored ContributorProblem with flash programmer
Hi,
I am sure it is a beginner problem but I am not able to find an answer in the help of NiosII. I would like to program my FPGA (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) with a .sof file. So I create a new project hello_world with a niosII_stratixII_2s60\full_featured SOPC builder. then I go to the flas progammer, I choose my project. Project and SOPC builder are recognized. Then I select the box "Program FPGA configuration data into harware-image region of flash memory". I disselect "Program software project into flash memory). I choose my .sof file Then I choose my hardware Image, I have two choices: factory U5+0xC00000 or user: U5 + 0x800000. I choose the second ( but it dosnt work with the 2 configurations). I switch on my board, Then I click on Program flash. Building and conversion to flah file are OK. then he tells me:"# Programming flash with the FPGA configuration
$SOPC_KIT_NIOS2/bin/nios2-flash-programmer --device=1 --sidp=0x021108C8 --id=203
2497071 --timestamp=1145613411 --base=0x00000000 full_featured.flash
There are no Nios II processors available which match the values specified.
Please check that your PLD is correctly configured, downloading a new SOF
file if necessary. "Probable Cause
The flash programmer is unable to connect with a Nios II JTAG debug
module inside the FPGA.
Suggested Actions
■ Make sure that the FPGA is running a valid flash programmer target
design. If not, you need to configure the FPGA using the Quartus II
programmer. See “Flash Programmer Target Design” on page 1–3.19 Replies
Altera_ForumI expected, that you are accessing EPCS through JTAG cause you are converting to jic format. In this case a particular SFL (serial flash loader) Megafunction would been included to your design (hopefully). I reported a case where this megafunction wasn't operational although included correctly to the design. But I'm not sure about your design, but I can't imagine how the EPCS design could be programmed through JTAG without having a serial flash loader.
P.S.: If a similar serial flash loader function is also imported by SOPC builder but it doesn't work as expected, it may be meaningful to try loading the EPCS through a standalone serial flash loader as described in the serial flash loader documentations (AN370).- Altera_Forum
You are right, now it works2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new.
I am sorry, but I have not all understood. What´s SFL? I don´t understand what you purpose me to do: I tried to send the .jic file with the Quartus II programmer, and I have this error:However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes.
I tried to send the .sof and the .jic but I have this error:Error: Can't configure device. Expected JTAG ID code 0x020930DD for device 1, but found JTAG ID code 0x120930DD.
But I am not sure it was what you meanError: Device chain in Chain Description File does not match physical device chain -- expected 2 device(s) but found 1 device(s). - Altera_Forum
I have two comments.
1. with Cyclone III, I sometimes experienced the PFL IP not working correct within the current design for unclear reasons, also reporting can't recognize silicon id for device 1. It turned out, that the AS pins didn't operate as they should in this situation. In one project, that initially could use SFL with Quartus 7.2, it didn't work any more after upgrading to SP3 to support CIIIC16. I suspect that there is a Quartus bug. However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes. 2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new. - Altera_Forum
Currently, I always am not able to make a non volatile configuration. Always the same mistake occures:
Can someone help me?? ThanksError: Can't recognize silicon ID for device 1 - Altera_Forum
i have only some vhdl code, i have written this code in quartus, but in the help they say to use flash programmer for a non-volatile configuration. so i jus use a hello_world project to have a project but i don´t cate about what this program does. i just want to load my .sof file.
If you only have some VHDL code, there is no need to add a Nios cpu in SOPC Builder, you can delete it, if it's already there or at least, if you need it as avalon master, use the smallest Nios cpu ('e'). This will reduce your configuration size, too. Without Nios cpu, you don't need any Nios program either. but i want more than every reset, i want to have my configuration even if i power down the board. Sorry, I wrote it imprecise, if you program the flash with a .jic-file, of course you will also have the configuration present after power down, it will be reloaded automatically from flash with the next power up. i don´t know what that is. i am forced to use epcs64 for flash device because for the others configuration he told me there is not enough memory ( my .sof file is 1.886 kb and the .jic file 8.193 kb ). actually, the epcs16 could be well but he doesn´t want.... In 'Convert Programming Files...' you could go to 'Options' and click 'Compression Mode', but I've never tried, maybe first read some documentation about that. error: can't recognize silicon id for device 1 I saw that error already, but sorry, I don't remember what was wrong that time. Maybe somebody else can answer this or you can find an answer in this forum. But first you could try the things described, maybe then this error is cleared. i think my pin assignments are right because when i load my .sof file it works. I also think so, it was just a general comment to that error message. - Altera_Forum
Thanks for your tips
I have only some VHDL code, I have written this code in Quartus, but in the Help they say to use Flash Programmer for a non-volatile configuration. So i jus use a hello_world project to have a project but I don´t cate about what this program does. I just want to load my .sof file.Why did you uncheck 'Program software project into flash memory'? Is there no Nios II program you want to load? If so, you could use the Quartus Programmer instead of the Flash programmer.
But i want more than every reset, i want to have my configuration even if I power down the board. I´ve tried but this error always occure:For only loading a .sof file to the flash, you can go to File-> Convert Programming Files..-> choose e.g. .jic File as programming file type -> choose the right flash device -> click on Flash Loader and choose your FPGA type -> click on SOF Data and choose your .sof-file -> generate. Then in the Quartus Programmer you can choose that .jic File and start programming the Quartus. Every reset of your board the configuration will be loaded from the flash into your FPGA, because you added a Flash Loader.
I don´t know what that is. I am forced to use EPCS64 for flash device because for the others configuration he told me there is not enough memory ( my .sof file is 1.886 KB and the .jic file 8.193 KB :eek: ). Actually, the EPCS16 could be well but he doesn´t want....Error: Can't recognize silicon ID for device 1
I think my pin assignments are right because when I load my .sof file it works.BTW, I got that 'There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.' message for several reasons already. Once I had some wrong clk assignements in the SOPC Builder, or in the Assignement Editor, or one of my user components have not been programmed well yet. In all that cases I got that message, just because the FPGA configuration was 'bad'. And sometimes it helped just to shut down the Nios IDE and the Quartus, or sometimes it was enough to only close and reopen the Quartus Programmer or once it helped to restart the PC. But the real reason for that message was one of the errors descriped before, what turned out later. Same happened to a colleage. Just to be complete about that error message. - Altera_Forum
Why did you uncheck 'Program software project into flash memory'? Is there no Nios II program you want to load? If so, you could use the Quartus Programmer instead of the Flash programmer.
For only loading a .sof file to the flash, you can go to File-> Convert Programming Files..-> choose e.g. .jic File as programming file type -> choose the right flash device -> click on Flash Loader and choose your FPGA type -> click on SOF Data and choose your .sof-file -> generate. Then in the Quartus Programmer you can choose that .jic File and start programming the Quartus. Every reset of your board the configuration will be loaded from the flash into your FPGA, because you added a Flash Loader. BTW, I got that 'There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.' message for several reasons already. Once I had some wrong clk assignements in the SOPC Builder, or in the Assignement Editor, or one of my user components have not been programmed well yet. In all that cases I got that message, just because the FPGA configuration was 'bad'. And sometimes it helped just to shut down the Nios IDE and the Quartus, or sometimes it was enough to only close and reopen the Quartus Programmer or once it helped to restart the PC. But the real reason for that message was one of the errors descriped before, what turned out later. Same happened to a colleage. Just to be complete about that error message. - Altera_Forum
Ok, I have loaded my program with the Quartus programmer and then redone what I described before.........
But that does not work :( Always the same mistake - Altera_Forum
If I'm not mistaken, I think you have to have the firmware (with NIOS core) programmed into the FPGA at least once before you can program using this method. So, program your sof file using the Quartus programmer for the very first time and then repeat what you have done. Once the NIOS firmware is in FLASH and can be booted at power-on, you should be OK.
