2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new.
You are right, now it works
However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes.
I am sorry, but I have not all understood. What´s SFL?
I don´t understand what you purpose me to do:
I tried to send the .jic file with the Quartus II programmer, and I have this error:
Error: Can't configure device. Expected JTAG ID code 0x020930DD for device 1, but found JTAG ID code 0x120930DD.
I tried to send the .sof and the .jic but I have this error:
Error: Device chain in Chain Description File does not match physical device chain -- expected 2 device(s) but found 1 device(s).
But I am not sure it was what you mean
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