Honored Contributor
Honored ContributorI have two comments.
1. with Cyclone III, I sometimes experienced the PFL IP not working correct within the current design for unclear reasons, also reporting can't recognize silicon id for device 1. It turned out, that the AS pins didn't operate as they should in this situation. In one project, that initially could use SFL with Quartus 7.2, it didn't work any more after upgrading to SP3 to support CIIIC16. I suspect that there is a Quartus bug. However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes. 2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new.
