Problem with flash programmer

Sometimes it is useful to check 'Halt onchip configuration controller' in Options --> Programmer if your serial flash is empty

This is the answer of Altera support:

# Programming flash with the FPGA configuration
$SOPC_KIT_NIOS2/bin/nios2-flash-programmer --sidp=0x021108C8 --id=2032497071 --t
imestamp=1145613411 --base=0x00000000 training.flash
There are no Nios II processors available which match the values specified.
Please check that your PLD is correctly configured, downloading a new SOF
file if necessary.

Yes, the DSP Dev Kit is using a parallel flash rather than an EPCS, I wasn't aware of that fact. The standard PFL programming file would use a *.pof type instead of *.jic for serial flash loader, but I don't know what's the NIOS II flow.

Just a quick reset here:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sfl IS
	PORT
	(
		noe_in		: IN STD_LOGIC 
	);
END sfl;
ARCHITECTURE SYN OF sfl IS
	COMPONENT altserial_flash_loader
	GENERIC (
		enable_shared_access		: STRING;
		lpm_type		: STRING
	);
	PORT (
			noe	: IN STD_LOGIC 
	);
	END COMPONENT;
BEGIN
	altserial_flash_loader_component : altserial_flash_loader
	GENERIC MAP (
		enable_shared_access => "OFF",
		lpm_type => "altserial_flash_loader"
	)
	PORT MAP (
		noe => noe_in
	);
END SYN;

My blank SFL design looks like this

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sfl_3c16 IS
END sfl_3c16;
ARCHITECTURE RTL OF sfl_3c16 IS
COMPONENT sfl
  PORT
  (
    noe_in		: IN STD_LOGIC
  );
END COMPONENT;
BEGIN
  sfl_inst : sfl PORT MAP (
  noe_in	 => '0'
  );
END RTL;

I have followed step by step the AN370:

Two concurrent programming methods have been discussed in this thread:

I am accessing my EPCS through JTAG.