Problem with FIR II core

--- Quote Start ---

Hi Kaz,

I don't understand what you mean by "path". Probably we still misunderstood.

Let me try again:

1. I have single 16 bit, 288Hz data stream (it represents one analog signal acquired with 16bit ADC, clocked with 288MHz)

2. I want to filter this signal (in digital domain) using symmetrical FIR with 11 coefficients

3. My current system is implement such a way that I get four 16 bit samples from the stream at once. (This means that I get 4 samples each 72 MHz)

How would you approach this problem in Quartus ?

Regards

Dimitar

--- Quote End ---

ok your stream is 16 bits @ 288Msps but implemented as 4 parallel sections @ 72MHz

All you have to do is:

convert the 4 section to 288 speed (serialise the 4 sections and pass it to filter(one channel @ 288 clock rate and 288 sample rate)