Honored Contributor
Honored ContributorHi kaz,
It is still not clear to me. Lets me try I understand your block diagram first I have 16 bit data stream 288MHz sample rate [... s7 s6 s5 s4 s3 s2 s1 s0 ... ] lets assume s0 is old sample, s7 is more recent sample I get my stream in 64 bit packets like this ... [s3 s2 s1 s0] [s7 s6 s5 s4] ... those quads I get on each 72 Mhz tick 1. From DSP perspective what I want to achieve is to filter my 288Mhz data stream with simple single channel FIR filter https://alteraforum.com/forum/attachment.php?attachmentid=15769&stc=1 (Please see 1.png) to do this I need to serialize my quads In your "option 1" you suggest clk = 4 x72=288MHz ,so I think you suggest this structure? But why you suggest 4 channels then? I need a single 288MHz filter and not 4 independent filters. (In your suggesting I don't know what "sample rate = 72" would mean. I tested that this setup brings 16 bit avalon bus width.) 2. Your second suggestion seems to be something like this + output multiplexer: (Please see 2.png) Have I understood correctly? Do you suggest that i have to calculate the impulse response of the above 4 filters such that if i multiplex their outputs with 288mhz rate i get the result I am after? (Edit: In fact it should be not a MUX but a Summation block and the FIR clocks should be 25% shifted ... for now I am just trying to get the global picture ) On a DSP controller the block processing (processing the data stream chunk by chunk) is something very standard. I am surprised that this appear as something not standard in the FPGA world, or am I misunderstood? Thank you Dimitar
