Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

you have set input delays for FPGA2 on an arbitrary basis and got above tables for arrival times(the worst values to be taken as tSU/tH of FPGA2).

--- Quote End ---

And What if the tSU/tH become negative? Does it mean that something goes wrong?