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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
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Altera_Forum
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11 years ago

Thanks for your prompt response.

As you advised me in the previous posts, I want to know setup times & hold times of my IO:

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However in practice you can first set input delays of fpga2 at some convenient values and see report(datasheet) to find out tSU/tH achieved at input pins. Then go to fpga1 and set output delays accordingly taking board delays into account

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The only report that I found was Datasheet Report/Setup Times & Hold Times.

Setup Summary & Hold Summary only show setup & hold times of my clock, not IO.

To summarize my problem:

i want to know setup time & hold time of my ios. How can I have them? Timequest datasheet report? Or some other way?

If TimeQuest Datasheet Report is that, then is there any problem with negative t_su & t_h values? (These parameters are not slack)