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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Those tables are not final slack except that you have thought of them as slack.

They are to do with arrival times (neg for hold, pos for setup relevant to clk edge) and you don't need them now.

look at slack report => setup or hold summary or top failing paths. You can select these from TQ GUI directly without need for commands.

Normally if timing fails you get red coloured text as a warning and quartus reports timing failure at end of messages.