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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

When I run timequest and report datasheet, I get negative values for t_h; i.e. Hold Times. Is this reasonable?

For some synthesis, t_h is positive, when I change settings t_h becomes negative. Does it mean something is wrong?