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Honored ContributorProblem with Data Integrity & Clock between 2 FPGAs
Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_ForumHonored Contributor
Honored ContributorIf this is your first time with TimeQuest, Altera has some free training to get you started. Here's the introductory one:
http://www.altera.com/education/training/courses/odsw1115
