Forum Discussion
Altera_Forum
Honored Contributor
17 years agoThe example has the disadvantage of not being fully synchronous, causing timing violations und unpredictable results if the gate edge comes at the wrong moment. Gate has to be synchronized to the main clk domain to avoid these effects.
Furthermore, it doesn't work if the Gate signal is shorter than a clock period. Thus, I don't know if it's a solution to cbarberis problem. The original approach can be basically extended by a handshake signal to avoid the multiple driver issue.always @ (posedge Gate or posedge GateReset)
begin
if (GateReset)
temp <= 1'b0;
else
temp <= 1'b1;
end
always @ (posedge clk)
begin
if(temp == 1'b1)
begin
clk1 <= clk1 +1;
if (clk1 < CounterVal)
PulseOut <= 1'b1;
else
begin
GateReset <= 1;
PulseOut <= 1'b0;
clk1 <=0;
end
end
else
GateReset <= 0;
end