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Altera_Forum
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7 years ago

Problem With Basically Everything

Greetings, The following forms a basis for my lack of understanding how Atlera has any market share whatsoever. I present the following points of fact regarding tool usability: graphi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

I dunno, I don't have a problem with the Altera Quartus tools at all. I set them up to use a Makefile: 


DESIGN=MY_DESIGN_NAME
all:: generate report
generate::
    $(QUARTUS_BIN)/quartus_map $(DESIGN) --write_settings_files=off
    $(QUARTUS_BIN)/quartus_fit $(DESIGN) --write_settings_files=off --seed=1
    $(QUARTUS_BIN)/quartus_asm $(DESIGN) --write_settings_files=off
    $(QUARTUS_BIN)/quartus_sta $(DESIGN)
    $(QUARTUS_BIN)/quartus_sta -t generate_timing.tcl $(DESIGN) 10
    $(QUARTUS_BIN)/quartus_eda $(DESIGN) --write_settings_files=off -c $(DESIGN)
    $(QUARTUS_BIN)/quartus_cpf -c $(DESIGN).cof
report::
    @-echo ' '
    -egrep --color -i '\(+ violated\)' TQ_*.rpt
    @-echo ' '
    -egrep -vi '^this panel reports' TQ_fmax_summary.rpt
    @-echo ' '
clean::
    -rm -f $(DESIGN).*.rpt $(DESIGN).*.summary $(DESIGN).*.smsg $(DESIGN).map
    -rm -f $(DESIGN)_assignment_defaults.qdf TQ_*.rpt PLL*.txt meminit.txt
    -rm -f $(DESIGN).done $(DESIGN).map $(DESIGN).pof $(DESIGN).sof $(DESIGN).jic
    -rm -f $(DESIGN).pin $(DESIGN).jdi $(DESIGN).qws $(DESIGN).*.ddb $(DESIGN).sld
    -rm -rf db incremental_db simulation
#  the end

so to rebuild a design after changes I just go to my design directory and type 'make' ...

I do all my designs in verilog, and write my own .qsf and .sdc files manually via text editor to guide the placement and routing result.