--- Quote Start ---
O.K., I see, but it's a pure functional simulation problem.
In first clock cycle, uninitialized x(0) and x(1) are added to f(0) and f(1). You easily find the problem looking at all design nodes in simulation, not just the output.
You had saved your and my time by giving a clear problem description in your first post.
--- Quote End ---
yeah,but how to solve this sitiation,here is totally code
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_signed.all;
entity firlms is
generic(W1: integer :=8;
W2: integer :=16;
L: integer :=2);
port ( clk : in std_logic;
x_in: in std_logic_vector(W1-1 downto 0);
d_in: in std_logic_vector(W1-1 downto 0);
y_in : in std_logic_vector(W2-1 downto 0);
e_out,y_out,e1,y1:out std_logic_vector(W2-1 downto 0));
end firlms;
architecture Behavioral of firlms is
component mult
port ( dataa : in std_logic_vector(7 downto 0);
datab : in std_logic_vector(7 downto 0);
result : out std_logic_vector(15 downto 0));
end component;
subtype n1bit is std_logic_vector(W1-1 downto 0);
subtype n2bit is std_logic_vector(W2-1 downto 0);
type array_n1bit is array(0 to L-1) of n1bit;
type array_n2bit is array(0 to L-1) of n2bit;
signal d,k :n1bit;
signal emu : n1bit;
signal y,sxty:n2bit;
signal e,sxtd:n2bit;
signal x: array_n1bit;
signal f : array_n1bit :=((others=> (others=>'0')));
signal p,xemu:array_n2bit;
begin
dsxt:process(d)
begin
sxtd(7 downto 0)<=d;
for k in 15 downto 8 loop
sxtd(k)<=d(d'high);
end loop;
end process;
store:process
begin
wait until clk='1';
--y <= y_in;
d <= d_in;
x(0) <= x_in;
x(1) <= x(0);
f(0)<=f(0)+xemu(0)(15 downto 8);
f(1)<=f(1) +xemu(1)(15 downto 8);
end process store;
--y<=p(0)+p(1);
ysxt:process(y)
begin
sxty(8 downto 0)<=y(15 downto 7);
for k in 15 downto 9 loop
sxty(k)<=y(y'high);
end loop;
end process;
e<=sxtd-sxty;
emu<=e(8 downto 1);
mulgen2:for i in 0 to L-1 generate
fir: mult port map (dataa=>x(i),datab=>emu,result=>xemu(i));
end generate;
--y_out<="00000000"&xemu(1);
--e_out<="00000000"&xemu(0);
e1<="00000000"&f(1);
y1<="00000000"&f(0);
end Behavioral;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity mult is
port ( dataa : in std_logic_vector(7 downto 0);
datab : in std_logic_vector(7 downto 0);
result : out std_logic_vector(15 downto 0));
end mult;
architecture fpga of mult is
begin
result<=dataa*datab;
end fpga;
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