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Altera_Forum
Honored Contributor
Honored Contributorproblem with adaptive FIR ,i realy need your help
hi all guys,i'm freshmem in forum,i got a problem with my vhdl code about adaptive FIR filter.I try write by myself but it fail (simulate in modelsim-altera),so that i write agian based on "dsp with ...
Altera_ForumHonored Contributor
Honored ContributorO.K., I see, but it's a pure functional simulation problem.
In first clock cycle, uninitialized x(0) and x(1) are added to f(0) and f(1). You easily find the problem looking at all design nodes in simulation, not just the output. You had saved your and my time by giving a clear problem description in your first post.
