Forum Discussion
Altera_Forum
Honored Contributor
12 years agoO.K., I see, but it's a pure functional simulation problem.
In first clock cycle, uninitialized x(0) and x(1) are added to f(0) and f(1). You easily find the problem looking at all design nodes in simulation, not just the output. You had saved your and my time by giving a clear problem description in your first post.