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A simple test would show whether it is SDRAM bandwidth limited - once the code/data is cached lack of bandwidth wouldn't matter.
It might be caused by problems exiting reset. You'd need to be certain that the JTAG download (if that is what you are using) isn't asserting the global reset for each cpu.
I've used two cpus, in my case I exposed the nios 'soft reset', loaded all the code from a single image, removed the reset from one cpu and got that cpu to remove the other reset after it had done some global initialisation.
I'm downloading (and controlling things) via a PCIe (slave) -> Avalon master bridge.
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Dsl,
please how can i do the test to know if the problem come from a bandwidth limitation?
thank you
Honored Contributor
