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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with a 5-bit counter programme

Design a 5-bit up/down counter with synchronous counting, asynchronous preset and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The problem isnt with the code. I just tidied up your version. The problem is that you load 7 onto count_sig at the start of the simulation. P_load has preference over the clock. The problem lies with your testbench.