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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with a 5-bit counter programme

Design a 5-bit up/down counter with synchronous counting, asynchronous preset and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Yes, elsif rising_edge(clock) is fine, else how would you have asynchronous resets or loads?

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True. My second post is the same like "elsif rising_edge" but i never write it like that.