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Honored Contributor
Honored ContributorProblem with a 5-bit counter programme
Design a 5-bit up/down counter with synchronous counting, asynchronous preset and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is it possible that u can't place a rising_edge in a if - elsif structure. --- Quote End --- Yes, elsif rising_edge(clock) is fine, else how would you have asynchronous resets or loads?
