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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with a 5-bit counter programme

Design a 5-bit up/down counter with synchronous counting, asynchronous preset and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is it possible that u can't place a rising_edge in a if - elsif structure.

Re-write it as: 

if risin_edge ... then
if reset then 
count_value <= 0;
elsif load then 
count_value <= load_value
elsif count_up then
count_value <= count_value + 1;
elsif count_dwn then
count_value <= count_value -1;
end if;
end if;

i didn't read the whole text to forfill ur teachers question :)